Terms of Service

1. AI Generated Verilog Liability

The synthesizable Verilog generated by the Chipix AI Orchestrator is provided "as is". While our models achieve 99.99% logical determinism, final assertion sign-off prior to tape-out is the sole responsibility of the architect.

2. Compute Allocation

Massive parallel testbenches requested via the Cloud Platform tier are billed dimensionally by core-hour. Deliberate denial-of-service simulations (e.g., infinite loop assertions without clock constraints) will result in cluster termination.